This invention relates to non-volatile memories, and more particularly, to embedded memories for combination with other integrated circuitry.
Data in digital systems, such as computers, cell phones, automotive and industrial controllers, etc. is generally stored in volatile and non-volatile memories. Volatile storage refers to data that is only valid while power is maintained, while non-volatile memory will maintain data even without power. There are existing non-volatile memory solutions such as EPROM, EEPROM, and Flash memories as well as ROM. ROM is fabricated with a fixed data pattern, which can never be altered. ROM is useful, therefore, when the information to be stored is known at the time of manufacture. Many applications, however, need to store information during operation or after installation. Those that only need a small amount of operational storage, such as calibration data for analog settings and configuration data for digital systems that have built in flexibility, can utilize memory that can be written with the needed parameters determined during installation or during a calibration process and that can then be accessed to provide the stored parameters during future operations.
For this reason, it is often desirable to include with other integrated circuitry memory that can be written with data so that a single integrated circuit can provide both operational functions and the data storage functions. Usually, memory combined in such a integrated circuit is referred to as embedded memory, because the memory is added into the digital design. One difficulty, however, is that the processes utilized to manufacture memory circuitry may not be compatible with the processes used to manufacture the logic, control or other integrated circuitry.
EPROM, EEPROM and Flash memory are all types of memory that store information by writing to the device during operation and would, therefore, be desirable for embedded applications. However, these devices generally use a storage transistor that has a floating gate, and charge is added or subtracted from this floating gate to store the binary states. Problematically, these floating gate technologies are normally fabricated on processes specifically tailored to the floating gate implementations. And the manufacturing process to make these floating gate devices is more complicated and more costly than standard CMOS technology. In addition, the floating gate processes will generally produce a lower performance logic (or digital) device because the additional processing required for the floating gate devices will often cause changes (generally degradation) in the performance of the basic CMOS transistors. Thus, high performance digital devices and floating gate memories are typically not compatible within the same integrated circuit. For this reason, it is difficult to maintain a high performance digital system with Flash memory added to a single integrated circuit.
Non-volatile memory solutions have been fabricated as stand alone components for many years, and these solutions have utilized various memory cell structures. Early memories were made of arrays of fuses which could be selectively blown by high current. A fuse device typically refers to a device that starts as a low-resistance element (i.e., short circuit) and is made to be a high resistance element by some action, such as high current. This fuse method was often used in bipolar technology because high currents are needed for writing or to blow the fuse and because bipolar transistors can deliver large currents.
Antifuse devices were also developed for non-volatile data storage. An antifuse structure refers to a device that starts as a high value resistance and is altered (i.e., in writing) to have a much lower value of resistance. Since these devices work in reverse of fuse elements, they are called antifuse elements. Typically, antifuse elements require some particular manufacturing characteristics to permit the formation of devices that can be altered as antifuse devices. Problems with antifuse implementations have included reliability issues associated with large variations in the final resistance of different antifuse elements that had been written. Thus, the use of antifuse elements has been limited. Other antifuse devices have been developed that use special features of a manufacturing process to make an antifuse element, such as using oxide-nitride-oxide (ONO) as a dielectric in the antifuse elements. This ONO structure has been used in DRAM manufacturing processes, but this ONO structure has not been generally available in standard CMOS processes for other types of CMOS integrated circuits.
The present invention provides a method of utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements and related embedded memories. The non-volatile memory cells and associated programming methods of the present invention allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture other CMOS circuitry. The non-volatile memory cell structure and related programming methods and embedded memories of the present invention, therefore, provide a desirable solution for embedded memory architectures.
In one embodiment, the present invention is a method for utilizing one or more voltage gradients to guide dielectric breakdown in a non-volatile memory cell integratable with other CMOS circuitry. The method includes providing an antifuse element having a programming node such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses and such that the change in resistivity representing a change in logic state. In addition, the antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the one or more voltage pulses. The method further includes coupling a capacitor element to the programming node of the antifuse element where the capacitor element is configured to provide the one or more voltage pulses to the programming node. And finally, the method includes forming one or more voltage gradients within the antifuse element to guide a location for breakdown to occur within the dielectric layer.
In another embodiment, the present invention is a non-volatile memory cell integratable with other CMOS circuitry having one or more voltage gradients to guide dielectric breakdown. The cell includes an antifuse element having a programming node, a capacitor element coupled to the antifuse element, and two or more voltage levels coupled to the antifuse element to generate one or more voltage gradients. The antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses where the change in resistivity representing a change in logic state. In addition, the antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the one or more voltage pulses. The capacitor element is configured to provide the one or more voltage pulses to the programming node. And the voltage gradients help guide the location for breakdown to occur within the dielectric layer.
Still further, the present invention is an embedded non-volatile memory integrated with other CMOS circuitry having one or more voltage gradients to guide dielectric breakdown. The embedded memory includes a plurality of non-volatile memory cells and write circuitry coupled to the cells. Each cell includes an antifuse element having a programming node, a capacitor element coupled to the antifuse element, an access element coupled to the programming node, and two or more voltage levels coupled to the antifuse element to generate one or more voltage gradients. The antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses where the change in resistivity representing a change in logic state. In addition, the antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the one or more voltage pulses. The capacitor element is configured to provide the one or more voltage pulses to the programming node. The voltage gradients help guide the location for breakdown to occur within the dielectric layer. And the access element is configured to allow determination of the logic state for the antifuse element. The write circuitry is coupled to the capacitor elements of the plurality of non-volatile memory cells, and the write circuitry is configured to generate and to provide one or more voltage pulses to the capacitor elements.